Cortex-A53: Workarounds for 819472, 824069 and 827319

The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <[email protected]>

diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index 462ecc3e787ad9cfac18f50a2a4d8f4659f30473..e185aa176294c1e31b00e54f9e86a8df51c958df 100644 (file)
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -73,9 +73,18 @@ will enable it.
 
 For Cortex-A53, the following errata build flags are defined :
 
+-  ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
+   CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
+
+-  ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
+   CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
+
 -  ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
    CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
 
+-  ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
+   CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
+
 -  ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
    link time to Cortex-A53 CPU. This needs to be enabled for some variants of
    revision <= r0p4. This workaround can lead the linker to create ``*.stub``

diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 2aa6effc2a3571e53e1df8b5253fc6469486b92e..44044d40306bfef8db5e033e286dffc740a07b27 100644 (file)
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -71,7 +71,11 @@
 /* Data Cache set/way op type defines */
 #define DC_OP_ISW                      U(0x0)
 #define DC_OP_CISW                     U(0x1)
+#if ERRATA_A53_827319
+#define DC_OP_CSW                      DC_OP_CISW
+#else
 #define DC_OP_CSW                      U(0x2)
+#endif
 
 /*******************************************************************************
  * Generic timer memory mapped registers & offsets

diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index 64ddc86fe1e721b90c7633343dafa4d1cf8931da..cbac84b93af659a150da326decf5aebbd49227af 100644 (file)
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -328,7 +328,11 @@ DEFINE_BPIOP_FUNC(allis, BPIALLIS)
  */
 DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC)
 DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC)
+#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
+DEFINE_DCOP_PARAM_FUNC(cvac, DCCIMVAC)
+#else
 DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
+#endif
 
 /* Previously defined accessor functions with incomplete register names  */
 #define dsb()                  dsbsy()

diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index b9d1f9faeee44ba4b4e7c014cf4eb40d140532d6..f796ae868d48f3857c5ace9f643ecf32bcb6b343 100644 (file)
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -119,7 +119,11 @@
 /* Data cache set/way op type defines */
 #define DCISW                  U(0x0)
 #define DCCISW                 U(0x1)
+#if ERRATA_A53_827319
+#define DCCSW                  DCCISW
+#else
 #define DCCSW                  U(0x2)
+#endif
 
 /* ID_AA64PFR0_EL1 definitions */
 #define ID_AA64PFR0_EL0_SHIFT  U(0)

diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index e07db300b56c6c3651742da21111a9298ded3ad7..836d61ef25cb6f75436ec22ac8162f28d6025335 100644 (file)
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -113,6 +113,18 @@ static inline void tlbi ## _type(uint64_t v)                       \
 }
 #endif /* ERRATA_A57_813419 */
 
+#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
+/*
+ * Define function for DC instruction with register parameter that enables
+ * the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
+ */
+#define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type)   \
+static inline void dc ## _name(uint64_t v)                     \
+{                                                              \
+       __asm__("dc " #_type ", %0" : : "r" (v));               \
+}
+#endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
+
 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
@@ -143,11 +155,23 @@ DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
  ******************************************************************************/
 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
+#if ERRATA_A53_827319
+DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
+#else
 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
+#endif
+#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
+DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
+#else
 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
+#endif
 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
+#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
+DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
+#else
 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
+#endif
 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
 
 /*******************************************************************************

diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S
index 4975ec60dfb3e6c9ce32d559abe15508f616067f..6e3ff81798c8e5bea5f73499848ce5225fb05e06 100644 (file)
--- a/lib/cpus/aarch32/cortex_a53.S
+++ b/lib/cpus/aarch32/cortex_a53.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,6 +29,36 @@ func cortex_a53_disable_smp
        bx      lr
 endfunc cortex_a53_disable_smp
 
+       /* ---------------------------------------------------
+        * Errata Workaround for Cortex A53 Errata #819472.
+        * This applies only to revision <= r0p1 of Cortex A53.
+        * ---------------------------------------------------
+        */
+func check_errata_819472
+       /*
+        * Even though this is only needed for revision <= r0p1, it
+        * is always applied due to limitations of the current
+        * errata framework.
+        */
+       mov     r0, #ERRATA_APPLIES
+       bx      lr
+endfunc check_errata_819472
+
+       /* ---------------------------------------------------
+        * Errata Workaround for Cortex A53 Errata #824069.
+        * This applies only to revision <= r0p2 of Cortex A53.
+        * ---------------------------------------------------
+        */
+func check_errata_824069
+       /*
+        * Even though this is only needed for revision <= r0p2, it
+        * is always applied due to limitations of the current
+        * errata framework.
+        */
+       mov     r0, #ERRATA_APPLIES
+       bx      lr
+endfunc check_errata_824069
+
        /* --------------------------------------------------
         * Errata Workaround for Cortex A53 Errata #826319.
         * This applies only to revision <= r0p2 of Cortex A53.
@@ -59,6 +89,21 @@ func check_errata_826319
        b       cpu_rev_var_ls
 endfunc check_errata_826319
 
+       /* ---------------------------------------------------
+        * Errata Workaround for Cortex A53 Errata #827319.
+        * This applies only to revision <= r0p2 of Cortex A53.
+        * ---------------------------------------------------
+        */
+func check_errata_827319
+       /*
+        * Even though this is only needed for revision <= r0p2, it
+        * is always applied due to limitations of the current
+        * errata framework.
+        */
+       mov     r0, #ERRATA_APPLIES
+       bx      lr
+endfunc check_errata_827319
+
        /* ---------------------------------------------------------------------
         * Disable the cache non-temporal hint.
         *
@@ -253,7 +298,10 @@ func cortex_a53_errata_report
         * Report all errata. The revision-variant information is passed to
         * checking functions of each errata.
         */
+       report_errata ERRATA_A53_819472, cortex_a53, 819472
+       report_errata ERRATA_A53_824069, cortex_a53, 824069
        report_errata ERRATA_A53_826319, cortex_a53, 826319
+       report_errata ERRATA_A53_827319, cortex_a53, 827319
        report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
        report_errata ERRATA_A53_855873, cortex_a53, 855873
 

diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 332bad75f3d880ec61f5777570825ffdbbb344cb..f20082d2d6167b14b17e13a20c3c1986bbc76804 100644 (file)
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -42,6 +42,36 @@ func cortex_a53_disable_smp
        ret
 endfunc cortex_a53_disable_smp
 
+       /* ---------------------------------------------------
+        * Errata Workaround for Cortex A53 Errata #819472.
+        * This applies only to revision <= r0p1 of Cortex A53.
+        * ---------------------------------------------------
+        */
+func check_errata_819472
+       /*
+        * Even though this is only needed for revision <= r0p1, it
+        * is always applied due to limitations of the current
+        * errata framework.
+        */
+       mov     x0, #ERRATA_APPLIES
+       ret
+endfunc check_errata_819472
+
+       /* ---------------------------------------------------
+        * Errata Workaround for Cortex A53 Errata #824069.
+        * This applies only to revision <= r0p2 of Cortex A53.
+        * ---------------------------------------------------
+        */
+func check_errata_824069
+       /*
+        * Even though this is only needed for revision <= r0p2, it
+        * is always applied due to limitations of the current
+        * errata framework.
+        */
+       mov     x0, #ERRATA_APPLIES
+       ret
+endfunc check_errata_824069
+
        /* --------------------------------------------------
         * Errata Workaround for Cortex A53 Errata #826319.
         * This applies only to revision <= r0p2 of Cortex A53.
@@ -70,6 +100,21 @@ func check_errata_826319
        b       cpu_rev_var_ls
 endfunc check_errata_826319
 
+       /* ---------------------------------------------------
+        * Errata Workaround for Cortex A53 Errata #827319.
+        * This applies only to revision <= r0p2 of Cortex A53.
+        * ---------------------------------------------------
+        */
+func check_errata_827319
+       /*
+        * Even though this is only needed for revision <= r0p2, it
+        * is always applied due to limitations of the current
+        * errata framework.
+        */
+       mov     x0, #ERRATA_APPLIES
+       ret
+endfunc check_errata_827319
+
        /* ---------------------------------------------------------------------
         * Disable the cache non-temporal hint.
         *
@@ -304,7 +349,10 @@ func cortex_a53_errata_report
         * Report all errata. The revision-variant information is passed to
         * checking functions of each errata.
         */
+       report_errata ERRATA_A53_819472, cortex_a53, 819472
+       report_errata ERRATA_A53_824069, cortex_a53, 824069
        report_errata ERRATA_A53_826319, cortex_a53, 826319
+       report_errata ERRATA_A53_827319, cortex_a53, 827319
        report_errata ERRATA_A53_835769, cortex_a53, 835769
        report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
        report_errata ERRATA_A53_843419, cortex_a53, 843419

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 5eb03baa9f665afd4d19b9d15d1d4d7a5c3d4a6c..3dfb66f9b2061255ea9e4020be4d62b62c46d8e5 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -53,10 +53,22 @@ endif
 # These should be enabled by the platform if the erratum workaround needs to be
 # applied.
 
+# Flag to apply erratum 819472 workaround during reset. This erratum applies
+# only to revision <= r0p1 of the Cortex A53 cpu.
+ERRATA_A53_819472      ?=0
+
+# Flag to apply erratum 824069 workaround during reset. This erratum applies
+# only to revision <= r0p2 of the Cortex A53 cpu.
+ERRATA_A53_824069      ?=0
+
 # Flag to apply erratum 826319 workaround during reset. This erratum applies
 # only to revision <= r0p2 of the Cortex A53 cpu.
 ERRATA_A53_826319      ?=0
 
+# Flag to apply erratum 827319 workaround during reset. This erratum applies
+# only to revision <= r0p2 of the Cortex A53 cpu.
+ERRATA_A53_827319      ?=0
+
 # Flag to apply erratum 835769 workaround at compile and link time.  This
 # erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
 # workaround can lead the linker to create "*.stub" sections.
@@ -156,10 +168,22 @@ ERRATA_N1_1043202 ?=1
 # higher DSU power consumption on idle.
 ERRATA_DSU_936184      ?=0
 
+# Process ERRATA_A53_819472 flag
+$(eval $(call assert_boolean,ERRATA_A53_819472))
+$(eval $(call add_define,ERRATA_A53_819472))
+
+# Process ERRATA_A53_824069 flag
+$(eval $(call assert_boolean,ERRATA_A53_824069))
+$(eval $(call add_define,ERRATA_A53_824069))
+
 # Process ERRATA_A53_826319 flag
 $(eval $(call assert_boolean,ERRATA_A53_826319))
 $(eval $(call add_define,ERRATA_A53_826319))
 
+# Process ERRATA_A53_827319 flag
+$(eval $(call assert_boolean,ERRATA_A53_827319))
+$(eval $(call add_define,ERRATA_A53_827319))
+
 # Process ERRATA_A53_835769 flag
 $(eval $(call assert_boolean,ERRATA_A53_835769))
 $(eval $(call add_define,ERRATA_A53_835769))